Personal computers commonly use dynamic memory read/write chips that are addressed or selected as physical banks, the chips being arranged in single in-line memory modules (SIMMs). Row address strobe (RAS) signals are used to select the physical banks of memory. In a system with, for example, sixteen banks, sixteen unique RAS lines are required. Lower cost, high performance memory systems are designed to operate in a direct mode wherein only one RAS line is active at any one time. In contrast, higher cost, high performance memory systems are designed with a wider memory data path and operate in an interleaved mode so that two RAS lines are simultaneously active for two bank interleaving.
Typically a memory controller is connected between the memory and a microprocessor, a direct memory access (DMA) controller, and other devices which access the memory. One of the functions of a memory controller is to decode the addresses of the locations to be accessed and generate the appropriate RAS select signal(s) for activating the proper memory bank(s) in accordance with the mode (direct or interleaved) of operation. In the direct mode, a memory controller need only have one decoder per memory bank, whereas in the interleaved mode, the controller needs only one decoder per two banks, the banks being arranged in pairs. A memory controller that supports both modes must provide a decoding mechanism for both modes. Typically, this is done by using two sets of decoders, one set being one decoder per bank for direct mode and the other set being one decoder per pair of banks for interleaved mode. Additional decode logic is needed to select the appropriate set.